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LTC1411 Single Supply 14-Bit 2.5Msps ADC
FEATURES
s s s s s s s s s s s
DESCRIPTIO
Sample Rate: 2.5Msps 80dB S/(N + D) and 90dB THD at 100kHz fIN Single 5V Operation No Pipeline Delay Programmable Input Ranges Low Power Dissipation: 195mW (Typ) True Differential Inputs Reject Common Mode Noise Out-of-Range Indicator Internal or External Reference Sleep (1A) and Nap (2mA) Shutdown Modes 36-Pin SSOP Package
The LTC (R)1411 is a 2.5Msps sampling 14-bit A/D converter in a 36-pin SSOP package, which typically dissipates only 195mW from a single 5V supply. This device comes complete with a high bandwidth sample-andhold, a precision reference, programmable input ranges and an internally trimmed clock. The ADC can be powered down with either the Nap or Sleep mode for low power applications. The LTC1411 converts either differential or single-ended inputs and presents data in 2's complement format. Maximum DC specs include 2LSB INL and 14-bit no missing code over temperature. Outstanding dynamic performance includes 80dB S/(N + D) and 90dB THD at 100kHz input frequency. The LTC1411 has four programmable input ranges selected by two digital input pins, PGA0 and PGA1. This provides input spans of 1.8V, 1.27V, 0.9V and 0.64V. An out-of-the-range signal together with the D13 (MSB) will indicate whether a signal is over or under the ADC's input range. A simple conversion start input and a data ready signal ease connections to FIFOs, DSPs and microprocessors.
APPLICATIO S
s s s s s s
Telecommunications High Speed Data Acquisition Digital Signal Processing Multiplexed Data Acquisition Systems Spectrum Analysis Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
1 2 AIN+ AIN- REFOUT REFIN 5k 5k 5 REFCOM1 2k 2.5V BANDGAP REFERENCE
10
AVP
30
DVP
OVDD
29
86 80 74 68 62 56 50 44 38 32 26 20 14 10
OGND 28 D13
3 4
+ -
12
14-BIT ADC
14
OUTPUT DRIVERS INTERNAL CLOCK
D0 BUSY OTR
25 27 26
REFCOM2 6
X1.62/ X1.15
CONTROL LOGIC
S/(N + D) (dB)
* * *
7, 8, 9
AGND
11
AVM
36
SLP
35
NAP
34
PGA0
33
PGA1
32
CONVST
31
DGND
1411 BD
U
S/(N + D) and Effective Bits vs Input Frequency
14 13 12 11 10
W
U
EFFECTIVE BITS
100 1000 INPUT FREQUENCY (kHz)
10000
1411 TA02
1411f
1
LTC1411
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW AIN+ AIN- REFOUT REFIN REFCOM1 REFCOM2 AGND1 AGND2 AGND3 1 2 3 4 5 6 7 8 9 36 SLP 35 NAP 34 PGA0 33 PGA1 32 CONVST 31 DGND 30 DVP 29 OVDD 28 OGND 27 BUSY 26 OTR 25 D0 24 D1 23 D2 22 D3 21 D4 20 D5 19 D6
AVP = DVP = OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 6V Analog Input Voltage (Note 3) ... - 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) .................. - 0.3V to 10V Digital Output Voltage ............... - 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1411C ............................................... 0C to 70C LTC1411I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1411CG LTC1411IG
AVP 10 AVM 11 D13 (MSB) 12 D12 13 D11 14 D10 15 D9 16 D8 17 D7 18
G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125C, JA = 95C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note 7) (Note 8)
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. (Notes 5, 6)
CONDITIONS
q q q
MIN 14
TYP
MAX 2 16 24 60
UNITS Bits LSB LSB LSB LSB ppm/C
External Reference = 2.5V IOUT(REF) = 0 15
DY A IC ACCURACY
SYMBOL PARAMETER
TA = 25C (Note 5)
CONDITIONS 100kHz Input Signal 500kHz Input Signal 100kHz Input Signal, Up to 5th Harmonic 500kHz Input Signal, Up to 5th Harmonic 100kHz Input Signal 500kHz Input Signal S/(N + D) 74dB MIN TYP 80.0 77.5 - 90 - 82 90 82 1.0 0.66 MAX UNITS dB dB dB dB dB dB MHz LSBRMS
1411f
S/(N + D) Signal-to-Noise Plus Distortion Ratio THD Total Harmonic Distortion Peak Harmonic or Spurious Noise Full Linear Bandwidth Transition Noise
2
U
W
U
U
WW
W
WU
U
LTC1411
A ALOG I PUT
SYMBOL PARAMETER VIN
Analog Input Range (Note 9)
Common Mode Input Range CIN tACQ tAP tjitter CMRR Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio Input Leakage Current (Pins 1, 2)
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Load Regulation REFCOM2 Output Voltage REFIN Input Current CONDITIONS IOUT = 0 IOUT = 0 4.75V VDD 5.25V 0 IOUT 1mA
DIGITAL I PUTS A D DIGITAL OUTPUTS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. (Note 5)
SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Output Source Current Output Sink Current VDD = 4.75V, IO = - 10A VDD = 4.75V, IO = - 200A VDD = 4.75V, IO = 160A VDD = 4.75V, IO = 1.6mA VOUT = 0V VOUT = VDD
q q
POWER REQUIRE E TS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. (Note 5)
SYMBOL PARAMETER VDD IDD Supply Voltage Supply Current Nap Mode Sleep Mode Power Dissipation Nap Mode Sleep Mode CONDITIONS (Note 9)
q
PD
UW
U
U
U
U
U
U
TA = 25C (Note 5)
CONDITIONS (AIN+) - (AIN-), PGA0 = PGA1 = 5V (AIN+) - (AIN-), PGA0 = 5V, PGA1 = 0V (AIN+) - (AIN-), PGA0 = 0V, PGA1 = 5V (AIN+) - (AIN-), PGA0 = PGA1 = 0V AIN+ or AIN- Between Conversions (Sample Mode) During Conversions (Hold Mode) 0 10 4 100 7 1 0V < (AIN- = AIN+) < VDD 62 0.1 MIN TYP 1.8 1.27 0.9 0.64 VDD MAX UNITS V V V V V pF pF ns ns psRMS dB A
U
TA = 25C (Note 5)
MIN 2.480 TYP 2.500 15 0.01 2 4.05 250 MAX 2.520 UNITS V ppm/C LSB/ V LSB/mA V A
IOUT = 0, PGA0 = PGA1 = 5V REFIN = External Reference 2.5V
CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD, Except SLP, NAP (Note 11)
q q q
MIN 2.4
TYP
MAX 0.8 10
UNITS V V A pF V V
2 4.75 4.0 0.05 0.10 - 10 10 0.4
V V mA mA
MIN 4.75
TYP 39 2 1 195 10 5
MAX 5.25 65
UNITS V mA mA A mW mW W
1411f
NAP = 0V (Note 11) SLP = 0V
q
325
NAP = 0V SLP = 0V
3
LTC1411
TI I G CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ t0 t1 t2 t3 t4 t5 t6 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time SLP to CONVST Wake-Up Time NAP to CONVST Wake-Up Time CONVST Low Time CONVST to BUSY Delay Data Ready After BUSY CONVST High Time Aperture Delay of Sample-and-Hold
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. (Notes 5) (See Figures 11a, 11b)
CONDITIONS (Note 9)
q q
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, OGND, AVM and AGND wired together unless otherwise noted. Note 3: When these pin voltages are taken below AGND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA without latchup. Note 4: When these pin voltages are taken below AGND, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below AGND without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, PGA1 = PGA0 = 5V, fSAMPLE = 2.5MHz at 25C and t r = t f = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN- tied to an external 2.5V reference voltage.
TYPICAL PERFOR A CE CHARACTERISTICS
S/(N + D) vs Input Frequency
86 80 74 68 62 56 50 44 38 32 26 20 14 10 100 1000 INPUT FREQUENCY (kHz) 10000
1411 G01
S/(N + D) (dB)
62
DISTORTION (dB)
SNR (dB)
4
UW
UW
MIN 2.5
TYP 250 100 210 250
MAX 350
UNITS MHz ns ns ms ns ns ns ns ns ns
10F Bypass Capacitor at REFCOM2 Pin (Note 10) CL = 25pF (Note 10)
q q
20 12 7 20 7
Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Recommended operating conditions. Note 10: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best performance ensure that CONVST returns high within 20ns after conversion start of after BUSY rises. Note 11: SLP and NAP have an internal pull-down so the pins will draw approximately 7A when tied high and less than 1A when tied low.
Signal-to-Noise Ratio vs Input Frequency
86 80 74 68 56 50 44 38 32 26 20 14 10 100 1000 INPUT FREQUENCY (kHz) 10000
1411 G02
Distortion vs Input Frequency
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 10 100 1000 INPUT FREQUENCY (kHz) 10000
1411 G03
2ND
THD 3RD
1411f
LTC1411 TYPICAL PERFOR A CE CHARACTERISTICS
Spurious Free Dynamic Range vs Input Frequency
0 -10 -20 -30
DISTORTION (dB)
SINAD (dB)
-40 -50 -60 -70 -80 -90 -100 -110 10 100 1000 INPUT FREQUENCY (kHz) 10000
1411 G04
50 44 38 32 26 20 14 10 100 1000 INPUT FREQUENCY (kHz) 10000
1411 G05
INL (LSB)
Differential Nonlinearity vs Output Code
1.0 0.8 0.6
SUPPLY CURRENT (mA)
0.4
42 41 40 39 38 37 36
SUPPLY CURRENT (mA)
DNL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4096 8192 12288 OUTPUT CODE 16384
1411 G08
Histogram for 4096 Conversions
3500 3000 2500 2000 1500 1000 500 0 -1 0 CODE 1
1411 G13
AMPLITUDE (dB)
COUNTS
UW
S/(N + D) vs Input Frequency and Amplitude
86 80 74 68 62 56 -40dB -20dB 0dB 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
Integral Nonlinearity vs Output Code
0
4096
8192 12288 OUTPUT CODE
16384
1411 G07
Supply Current vs Temperature
45 44 43 VDD = 5V 46.5 44.0 41.5 39.0 36.5 34.0 31.5 -25 25 50 0 TEMPERATURE (C) 75 100
1411 G11
Supply Current vs Supply Voltage
TA = 25C
35 -50
4.5
4.75
5.0 VDD (V)
5.25
5.5
1411 G12
4096 Points FFT Plot (100kHz)
0 -20 -40 -60 -80 -100 -120 -140 0 250 500 750 1000 INPUT FREQUENCY (kHz) 1250
1411 G14
SINAD = 78.8dB SFDR = 95dB fSAMPLE = 2.5MHz fIN = 100kHz
1411f
5
LTC1411 TYPICAL PERFOR A CE CHARACTERISTICS
4096 Points FFT Plot (1MHz)
0 -20 -40 -60 -80 -100 -120 -140 0 250 500 750 1000 1250
1411 G15
ACQUISITION TIME (s)
SINAD = 75dB SFDR = 81dB fSAMPLE = 2.5MHz fIN = 1MHz
AMPLITUDE (dB)
PI FU CTIO S
AIN+ (Pin 1): Positive Analog Input. The ADC converts the difference voltage between AIN+ and AIN- with programmable input ranges of 1.8V, 1.27V, 0.9V and 0.64V depending on PGA selection. AIN+ has common mode range between 0V and VDD. AIN- (Pin 2): Negative Analog Input. This pin can be tied to the REFOUT pin of the ADC or tied to an external DC voltage. This voltage is also the bipolar zero for the ADC. AIN- has common mode range between 0V and VDD. REFOUT (Pin 3): 2.5V Reference Output. Bypass to AGND1 with a 22F tantalum capacitor if REFOUT is tied to AIN-. No capacitor is needed if the external reference is used to drive AIN-. REFIN (Pin 4): Reference Buffer Input. This pin can be tied to REFOUT or to an external reference if more precision is required. REFCOM1 (Pin 5): Noise Reduction Pin. Put a 10F bypass capacitor at this pin to reduce the noise going into the reference buffer. REFCOM2 (Pin 6): 4.05V Reference Compensation Pin. Bypass to AGND1 with a 10F tantalum capacitor in parallel with a 0.1F ceramic. AGND (Pins 7 to 9): Analog Ground. AGND1 is the ground for the reference. AGND2 is the ground for the comparator and AGND3 is the ground for the remaining analog circuitry. AVP (Pin 10): 5V Analog Power Supply. Bypass to AGND with a 10F tantalum capacitor. AVM (Pin 11): Analog and Digital Substrate Pin. Tie this pin to AGND. D13 to D0 (Pins 12 to 25): Digital Data Outputs. D13 is the MSB (Most Significant Bit). OTR (Pin 26): Out-of-the-Range Pin. This pin can be used in conjunction with D13 to determine if a signal is less than or greater than the analog input range. If D13 is low and OTR is high, the analog input to the ADC exceeds the maximum voltage of the input range. BUSY (Pin 27): Busy Output. Converter status pin. It is low during conversion. OGND (Pin 28): Digital Ground for Output Drivers (Data Bits, OTR and BUSY). OVDD (Pin 29): 3V or 5V Digital Power Supply for Output Drivers (Data Bits, OTR and BUSY). Bypass to OGND with a 10F tantalum capacitor.
1411f
6
UW
Acquisition Time vs Source Resistance
100
10
1
0.1
0.01
1
FREQUENCY (kHz)
10 1000 10000 100000 100 SOURCE RESISTANCE ()
1411 G16
U
U
U
LTC1411
PI FU CTIO S
DVP (Pin 30): 5V Digital Power Supply Pin. Bypass to OGND with a 10F tantalum capacitor. DGND (Pin 31): Digital Ground. CONVST (Pin 32): Conversion Start Signal. This active low signal starts a conversion on its falling edge. PGA1, PGA0 (Pins 33, 34): Logic Inputs for Programmable Input Range. This ADC has four input ranges (or four REFCOM2 voltages) controlled by these two pins. For the logic inputs applied to PGA0 and PGA1, the following summarizes the gain levels and the analog input range with AIN- tied to 2.5V.
Table 1. Input Spans for LTC1411
PGA0 5V 5V 0V 0V PGA1 5V 0V 5V 0V LEVEL 0dB - 3dB - 6dB - 9dB INPUT SPAN 1.8V 1.28V 0.9V 0.64V REFCOM2 VOLTAGE 4V 2.9V 2V 1.45V
TYPICAL CO
ECTIO DIAGRA
1 2
AIN+ AIN- REFOUT REFIN 5k 5k 2k INTERNAL CLOCK 2.5V BANDGAP REFERENCE
+
22F*
3 4
+ -
14-BIT ADC
+
10F
5
REFCOM1
+
10F
REFCOM2 6
X1.62/ X1.15
CONTROL LOGIC
7, 8, 9
AGND
11
AVM
36
SLP
35
NAP
34
PGA0
*A 22F CAPACITOR IS NEEDED IF REFOUT IS USED TO DRIVE AIN-
+
W
U
UU
U
U
U
NAP (Pin 35): Nap Input. Driving this pin low will put the ADC in the Nap mode and will reduce the supply current to 2mA and the internal reference will remain active. SLP (Pin 36): Sleep Input. Driving this pin low will put the ADC in the Sleep mode and the ADC draws less than 1A of supply current.
5V
10
AVP
30
DVP
OVDD
29
+
5V OR 3V
OGND 28 D13 12 14
OUTPUT DRIVERS
* * *
D0 BUSY OTR 25 27 26
33
PGA1
32
CONVST
31
DGND
1411 TA01
1411f
7
LTC1411
TEST CIRCUITS
Load Circuits for Access Timing
5V 1k DN 1k CL DN CL DN 1k CL DN CL
Load Circuits for Output Float Delay
5V 1k
(A) Hi-Z TO VOH AND VOL TO VOH
(B) Hi-Z TO VOL AND VOH TO VOL
1411 TC01
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
1411 TC02
APPLICATIO S I FOR ATIO
CONVERSION DETAILS
The LTC1411 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output. The ADC is complete with a precision reference, internal clock and a programmable input range. The device is easy to interface with microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversions are started by a falling edge on the CONVST input. Once a conversion cycle has begun, it cannot be restarted. Between conversions, the ADC acquires the analog input in preparation for the next conversion. In the acquire phase, a minimum time of 100ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal.
10 1 2 AIN+ AIN
-
AVP
30
DVP
+ -
INTERNAL CLOCK
14-BIT ADC
14
OUTPUT DRIVERS
CONTROL LOGIC
36
SLP
35
NAP
34
PGA0
33
PGA1
32
CONVST
31
DGND
1411 F01
Figure 1. Simplified Block Diagram
8
U
During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The input is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by a high speed comparator. At the end of a conversion, the DAC output balances the analog input (AIN+ - AIN-). The SAR contents (a 14-bit data word) which represents the difference of AIN+ and AIN- are loaded into the 14-bit output latches. DYNAMIC PERFORMANCE The LTC1411 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Figure 2a shows a typical LTC1411 FFT plot. Signal-to-Noise The signal-to-(noise + distortion) ratio [S/N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from the above DC and below half the sampling frequency. Figure 2a shows a typical spectral content with a 2.5MHz sampling rate and a 100kHz input. The dynamic performance holds well to higher input frequencies (see Figure 2b).
1411f
W
UU
OVDD
29
OGND 28 D13 12
* * *
D0 BUSY OTR 25 27 26
LTC1411
APPLICATIO S I FOR ATIO
0 -20 -40 -60 -80 -100 -120 -140 0 250 500 750 1000 INPUT FREQUENCY (kHz) 1250
1411 G14
SINAD = 78.8dB SFDR = 95dB fSAMPLE = 2.5MHz fIN = 100kHz
AMPLITUDE (dB)
S/(N + D) (dB)
Figure 2a. LTC1411 Nonaveraged, 4096 Point FFT, Input Frequency = 100kHz
0 -20 -40 -60 -80 -100 -120 -140 0 250 500 750 1000 1250
1411 G15
SINAD = 75dB SFDR = 81dB fSAMPLE = 2.5MHz fIN = 1MHz
AMPLITUDE (dB)
DISTORTION (dB)
FREQUENCY (kHz)
Figure 2b. LTC1411 4096 Point FFT, Input Frequency = 1MHz
Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOBS = [S/(N + D) - 1.76]/6.02 where S/(N + D) is expressed in dB. At the maximum sampling rate of 2.5MHz the LTC1411 maintains good ENOBs up to the Nyquist input frequency of 1.25MHz. Refer to Figure 3. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental
U
86 80 74 68 62 56 50 44 38 32 26 20 14 10 100 1000 INPUT FREQUENCY (kHz) 10000
1411 TA02
W
UU
14 13 12 11 10
Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 10 100 1000 INPUT FREQUENCY (kHz) 10000
1411 G03
EFFECTIVE BITS
2ND
THD 3RD
Figure 4. Distortion vs Input Frequency
itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:
V + V3 + V4 + ... VN THD = 20 log 2 V1
2
2
2
2
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. THD vs input frequency is shown in Figure 4. The LTC1411 has good distortion performance up to the Nyquist frequency and beyond.
1411f
9
LTC1411
APPLICATIO S I FOR ATIO
Peak Harmonic or Spurious Noise
ACQUISITION TIME (s)
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in dB relative to the RMS value of a fullscale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 74dB (12 effective bits). The LTC1411 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter's Nyquist frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The differential analog inputs of the LTC1411 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN- input is tied to a fixed DC voltage such as the REFOUT pin of the LTC1411 or an external source). Figure 1 shows a simplified block diagram for the analog inputs of the LTC1411. The AIN+ and AIN- are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuits is low, then the LTC1411 inputs can be driven directly. More acquisition time should be allowed for a higher impedance source. Figure 5 shows the acquisition time versus source resistance. Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging
10
U
100 10 1 0.1 0.01 1 10 1000 10000 100000 100 SOURCE RESISTANCE ()
1411 G16
W
UU
Figure 5. Acquisition Time vs Source Resistance
the sampling capacitor, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1411 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1411. More detailed information is available in the Linear Technology Databooks and on the LinearViewTM CD-ROM. LT(R)1227: 140MHz Video Current Feedback Amplifier. 10mA supply current. 5V to 15V supplies. Low noise. Good for AC applications. LT1395: 400MHz Current Feedback Amplifier. Single 5V or 5V supplies. Good for AC applications. LT1800: 80MHz, 25V/s Low Power Rail-to-Rail Input and Output Precision Op Amp. Specified at 3V, 5V and 5V supplies. Excellent DC performance.
LinearView is a trademark of Linear Technology Corporation.
1411f
LTC1411
APPLICATIO S I FOR ATIO
LT6203: Dual 100MHz, Low Noise, Low Power Op Amp. Specified at 3V, 5V and 5V supplies. 1.9nV/Hz noise voltage. Programmable Input Range The LTC1411 has two logic input pins (PGA0 and PGA1) that are used to select one of four analog input ranges. These input ranges are set by changing the reference voltage that is applied to the internal DAC of the ADC (REFCOM2). For the "0dB" setting the internal DAC sees the full reference voltage of 4V. The analog input range is 0.7V to 4.3V with AIN- = 2.5V. This corresponds to an input span of 1.8V with respect to the voltage applied to AIN- . For the "- 3dB" setting the internal reference is reduced to 0.707 * 4V = 2.9V. Likewise the input span is reduced to 1.28V. The following table lists the input span with respect to AIN- for the different PGA0 and PGA1 settings.
Table 1. Input Spans for LTC1411
PGA0 5V 5V 0V 0V PGA1 5V 0V 5V 0V LEVEL 0dB - 3dB - 6dB - 9dB INPUT SPAN 1.8V 1.28V 0.9V 0.64V REFCOM2 VOLTAGE 4V 2.9V 2V 1.45V
When changing from one input span to another, more time is needed for the REFCOM2 pin to reach the correct level because the bypass capacitor on the pin needs to be charged or discharged. Figure 6 shows the recommended capacitors at the REFCOM1 and REFCOM2 pins (10F each). When - 6dB or - 9dB is selected, the voltage at REFCOM1 (see Figure 2) must first settle before REFCOM2 reaches the correct level. The typical delay is about 700ms. When the REFCOM2 level is changed from 2.9V to 4V (changing PGA setting from - 3dB to 0dB), the typical delay is 0.6ms. However, if the voltage at REFCOM2 is changed from 4V to 2.9V (changing PGA setting from 0dB to - 3dB) only a 60A sink current is present to discharge the 10F bypass capacitor. In this case, the delay will be 11ms.
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Internal Reference The LTC1411 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V. If this REFOUT pin is used to drive the AIN- pin, a 22F tantalum bypass capacitor is required and this REFOUT voltage sets the bipolar zero for the ADC. The REFIN pin is connected to the reference buffer through a 2k resistor and two PGA switches. The REFIN pin can be connected to REFOUT directly or to an external reference. Figure 6 shows the reference and buffer structure for the LTC1411. The input to the reference buffer is either REFIN or 1/2 of REFIN depending on the PGA selection. The REFCOM1 pin bypassed with a 10F tantalum capacitor helps reduce the noise going into the buffer. The reference buffer has a gain of 1.62 or 1.15 (depends on PGA selection). It is compensated at the REFCOM2 pin with a 10F tantalum capacitor. The input span of the ADC is set by the output voltage of this REFCOM2 voltage. For a 2.5V input at the REFIN pin, the REFCOM2 will have 4V output for PGA1 = PGA0 = 5V and the ADC will have a span of 3.6V.
REFOUT 2.5V BANDGAP REFERENCE 22F** REFIN* 5k 5k REFCOM1 2k 10F REFCOM2 X1.62 10F
1411 F06
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*THIS PIN CAN BE TIED TO REFOUT OR AN EXTERNAL SOURCE **A 22F CAPACITOR IS NEEDED IF REFOUT IS USED TO DRIVE AIN-
Figure 6. Reference Structure for the LTC1411 for PGA1 = PGA0 = 5V
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LTC1411
APPLICATIO S I FOR ATIO
Figure 7 shows a typical reference, the LT1019A-2.5 connected to the LTC1411. This will provide an improved drift (equal to the maximum 5ppm/C of the LT1019A-2.5).
5V INPUT RANGE: 0.7V TO 4.3V 5V 2 VIN VOUT LT1019A-2.5 GND 4 6 3 10F 1 2 4 LTC1411 AIN+ AIN- REFIN AGND 7, 8, 9
1411 F07
Figure 7. Supplying a 2.5V Reference Voltage to the LTC1411 with the LT1019A-2.5
Digital Interface The ADC has a very simple digital interface with only one control input, CONVST. A logic low applied to the CONVST input will initiate a conversion. The ADC presents digital data in 2's complement format with bipolar zero set by the voltage applied to the AIN- pin. Internal Clock The internal clock is factory trimmed to achieve a typical conversion time of 260ns. With the typical acquisition time of 100ns, a throughput sampling rate of 2.5Msps is guaranteed. Out-of-the-Range Signal (OTR) The LTC1411 has a digital output, OTR, that indicates if an analog input signal is out of range. The OTR remains low when the analog input is within the specified range. Once the analog signal goes to the most negative input (1000 0000 0000 00) or 64LSB above the specified most positive input, OTR will go high. By NORing D13 (MSB) and its complement with OTR, overrange and underrange can be detected as shown in Figure 8. Table 2 is the truth table of the out-of-the-range circuit in Figure 8. Power Shutdown (Sleep and Nap Modes) The LTC1411 provides two shutdown features that will save power when the ADC is inactive.
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OTR D13 U1-A "1" FOR OVERRANGE D13 U1-B "1" FOR UNDERRANGE U1-A, U1-B = 74HC OR EQUIVALENT
1411 F08
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Figure 8. Overrange and Underrange Logic Table 2. Out-of-the-Range Truth Table
OTR 0 0 1 1 D13 (MSB) 0 1 0 1 ANALOG INPUT In Range In Range Overrange Underrange
NAP t1 CONVST
1411 F09
Figure 9. NAP to CONVST Wake-Up Timing
By driving the SLP pin low for Sleep mode, the ADC shuts down to less than 1A. After release from the Sleep mode, the ADC needs 210ms (10F bypass capacitor on the REFCOM2 pin) to wake up. In Nap mode, all the power is off except the internal reference which is still active for the other external circuitry. In this mode the ADC draws about 2mA instead of 39mA (for minimum power, the logic inputs must be within 600mV from the supply rails). The wake-up time from Nap mode to active state is 250ns as shown in Figure 9. Board Layout and Bypassing Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1411, a printed circuit board with a ground plane is required. Layout for the printed circuit board should ensure that the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track.
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LTC1411
APPLICATIO S I FOR ATIO
An analog ground plane separate from the logic system ground should be established under and around the ADC. AGND1, 2, 3 (Pins 7 to 9), AVM (Pin 11), DGND (Pin 31) and OGND (Pin 28) and all other analog grounds should be connected to a single analog ground point. The REFOUT, REFCOM1, REFCOM2 and AVP should bypass to this analog ground plane (see Figure 10). No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. Timing and Control Conversion start is controlled by the CONVST digital input. The falling edge transition of the CONVST will start a conversion. Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. The digital output code is updated at the end of conversion about 7ns after BUSY rises, i.e., output data is not valid on the rising edge of BUSY. Valid data can be latched with the falling edge of BUSY or with the rising edge of CONVST. In either case, the data latched will be for the previous conversion results. Figures 11a and 11b are the timing diagrams for the LTC1411.
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AIN+ LTC1411 AIN- REFOUT REFIN REFCOM1 REFCOM2 AGND1 AGND2 AGND3 AVM AVP DVP OVDD DGND OGND 3 4 5 6 7 8 9 11 10 30 29 31 28
ANALOG INPUT CIRCUITRY
+ -
2
Figure 10. Power Supply Grounding Practice
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3V Input/Output Compatible The LTC1411 operates on a 5V supply, which makes the device easy to interface to 5V digital systems. This device can also talk to 3V digital systems: the digital input pins (CONVST, NAP and SLP) of the LTC1411 recognize 3V or 5V inputs. The LTC1411 has a dedicated output supply pin (OVDD) that controls the output swings of the digital output pins (D0 to D13, BUSY and OTR) and allows the part to talk to either 3V or 5V digital systems. The output is two's complement binary. Figure 12 is the input/output characteristics of the ADC when AIN- = 2.5V. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB... FS - 1.5LSB). The output code is scaled such that 1LSB = FS/16384 = 3.6V/16384 = 219.7V. Offset and Full-Scale Adjustment In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 13 shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN- input. For zero offset error, apply 2.49989V (i.e., - 0.5LSB) at AIN+ and adjust R2 at the AIN- input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. For full-scale adjustment, an input voltage of 4.29967V (FS - 1.5LSBs) is applied to AIN+ and R5 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11.
DIGITAL SYSTEM
1411 F10
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LTC1411
APPLICATIO S I FOR ATIO
t CONV (SAMPLE N) t2 CONVST
t3 BUSY
DATA
DATA (N - 1) DB13 TO DB0
Figure 11a. CONVST Starts a Conversion with a Short Active Low Pulse
t5 (SAMPLE N) CONVST t3 BUSY
tCONV
DATA
DATA (N - 1) DB13 TO DB0
Figure 11b. CONVST Starts a Conversion with a Short Active High Pulse
011...111 011...110 BIPOLAR ZERO
OUTPUT CODE
000...001 000...000 111...111 111...110
100...001 100...000 -FS/2 1LSB = FS = 3.6V = 219.7V 16384 16384 -1 2.5V 1 FS/2 - 1LSB LSB LSB INPUT VOLTAGE (V)
1411 F12
Figure 12. LTC1411 Bipolar Transfer Characteristics (2's Complement)
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t ACQ t4 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0
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t5
t3
t ACQ
t4 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0
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R7 51 R1 51 5V OFFSET ADJUST R2 10k 5V R4 100k R5 FULL-SCALE ADJUST 750 R6 100k R3 51k
AIN+ AIN-
LTC1411
REFIN
1411 F13
Figure 13. Offset and Full-Scale Adjustment
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LTC1411
PACKAGE DESCRIPTIO
5.20 - 5.38** (.205 - .212)
.13 - .22 (.005 - .009)
.55 - .95 (.022 - .037)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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G Package 36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.67 - 12.93* (.499 - .509) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 7.65 - 7.90 (.301 - .311) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1.73 - 1.99 (.068 - .078) 0 - 8 .65 (.0256) BSC .25 - .38 (.010 - .015) .05 - .21 (.002 - .008)
G36 SSOP 0501
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LTC1411
TYPICAL APPLICATIO
PROGRAMMABLE RANGE DIFFERENTIAL INPUTS (0.64V TO 1.8V)
1 2 3 4
AIN+ AIN- REFOUT REFIN 5k 5k 2k INTERNAL CLOCK 2.5V BANDGAP REFERENCE
+ -
14-BIT ADC
+
10F
5
REFCOM1
+
10F
REFCOM2 6
X1.62/ X1.15
CONTROL LOGIC
7, 8, 9
AGND
11
AVM
36
SLP
35 5V
NAP
34
PGA0
RELATED PARTS
PART NUMBER 16-Bit LTC1608 14-Bit LTC1414 LTC1419 LTC1744 12-Bit LTC1420 LTC1412 LTC1402 LTC1405 LTC1410 LTC1415 12 12 12 12 12 12 10Msps 3Msps 2.2Msps 5Msps 1.25Msps 1.25Msps 5V or 5V Supply, 71dB SINAD and Input PGA 150mW, 71dB SINAD and 84dB THD 90mW, Serial Interface, 16-Lead SSOP Package 115mW, 71.3dB S/N+D, 85dB SFDR 150mW, 71.5dB SINAD and 84dB THD 55mW, Single 5V Supply 14 14 14 2.2Msps 800ksps 50Msps 150mW, 81dB SINAD and 95dB SFDR 150mW, 81.5dB SINAD and 95dB SFDR 1.5W, Two Modes: 77dB SNR or 90dB SFDR 16 500ksps 2.5V Input Range, Pin Compatible with LTC1604 RESOLUTION SPEED COMMENTS
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
www.linear.com
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2.5Msps 14-Bit ADC with Programmable Input Range
5V 10 AVP 30 DVP OVDD 29
+
5V OR 3V
OGND 28 D13 14 12 14-BIT OUTPUT DATA 25 27 26
OUTPUT DRIVERS
* * *
D0 BUSY OTR
33
PGA1
32
CONVST
31
DGND
1411 TA03
2.5MHz CONVERT INPUT INPUT RANGE SELECTION
1411f LT/TP 0902 2K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2001

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